RSD ASIC Chip designed using APsystems’ IP with redundancy topology Highly integrated SoC System on a chip design for lowest component count. No DC:DC power conversion for the solar power. Therefore much higher MTBF compared to optimizer based systems.
Longer daily module operating period (15 ~ 30 minutes) due to its low minimum operation voltage (8V) Does not interfere with global MPP tracking algorithms and shade mitigation algorithms e.g. SMA ShadeFix Very Low power consumption
Eliminates Unwanted AFCI Nuisance Tripping, approved and tested by SMA and Fronius RSD-S-PLC Noise Spectrum Density is far away (isolated) from typical AFCI noise patterns